EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 458

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

I/O Timing
1–48
Cyclone III Handbook
Notes to
(1)
(2)
(3)
Input Delay
from Pin to
Internal
Cells
Input Delay
from Pin to
Input
Register
Delay from
Output
Register to
Output Pin
Parameter
Table 1–46. Cyclone III IOE Programmable Delay on Column Pins (1),
The incremental values for the settings are generally linear. For exact values of each setting, please use the latest version of
Quartus III software.
The minimum and maximum offset timing numbers are in reference to setting "0" as available in the Quartus II software.
The fast corner timing parameter is for commercial devices.
Table
Pad -> I/O
dataout to
core
Pad -> I/O
input
register
I/O output
register ->
Pad
1–46:
Affected
Paths
Settings
Number
IOE Programmable Delay
Table 1–46
devices.
of
7
8
2
Fast Corner
Offset
Min
and
0
0
0
Table 1–47
Offset
2344
2788
Max
318
(3)
-6 Speed Grade
Offset
show IOE programmable delay for Cyclone III
Min
0
0
0
Offset
3827
4555
Max
563
(2)
-7 Speed Grade
Offset
Altera Corporation- Preliminary
Min
0
0
0
Offset
4088
4748
Max
617
-8 Speed Grade
Offset
Min
0
0
0
March 2007
Offset
4349
4940
Max
670
Unit
ps
ps
ps