EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 257

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 10–4. Multi-Device AS Configuration
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Altera Corporation-Preliminary
March 2007
Serial Configuration
Connect the pull-up resistors to V
Connect the pull-up resistor to the V
You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device’s nCE pin
The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the
Cyclone III master device in AS mode and the slave devices in PS mode. To connect MSEL[3..0] for the master
device in AS mode, refer to
refer to
These are dual-purpose I/O pins. FLASH_nCE pin functions as the nCSO pin in AS configuration scheme. DATA[1]
pin functions as the ASDO pin in AS configuration scheme.
Connect the series resistor at the near end of the serial configuration device.
Connect the repeater buffers between the Cyclone III master and slave device(s) for DATA[0] and DCLK. All I/O
inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers has to fit the
maximum overshoot equation outlined in
Device
Figure
DCLK
DATA
ASDI
nCS
10 kΩ
Table 10–10 on page
V
CCIO
10–4:
25 Ω (6)
(1)
10 kΩ
V
CCIO
(1)
1
10 kΩ
Table 10–6 on page
10–46. Connect the MSEL pins directly to V
V
GND
CCIO
CCIO
(1)
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
FLASH_nCE (5)
DATA[1] (5)
CCIO
Cyclone III Master Device
Buffers (7)
When connecting a serial configuration device to the Cyclone III
device in multi-device AS configuration, you must connect a
25
device for the DATA[0]. Additionally, you must connect the
repeater buffers between the Cyclone III master and slave
device(s) for DATA[0] and DCLK. All I/O inputs must maintain
a maximum AC voltage of 4.1 V. The output resistance of the
repeater buffers has to fit the maximum overshoot equation
outlined in
page
supply of the bank the pin resides in.
supply voltage of I/O bank that the nCEO pin resides in.
Ω
“Configuration and JTAG Pin I/O Requirements” on page
series resistor at the near end of the serial configuration
10–13.
10–15. To connect MSEL[3..0] for the slave devices in PS mode,
Active Serial Configuration (Serial Configuration Devices)
MSEL[3..0]
“Configuration and JTAG Pin I/O Requirements” on
nCEO
10 kΩ
(4)
V
CCIO
Cyclone III Device Handbook, Volume 1
CCIO
(2)
or GND.
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Cyclone III Slave Device
MSEL[3..0]
nCEO
10–13.
10–21
N.C. (3)
(4)