EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 179

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 7–14. Cyclone III Device I/O Banks
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Altera Corporation-Preliminary
March 2007
This is a top view of the silicon die. This is a graphic representation only. Refer to the pin list and the Quartus II
software for exact pin locations.
Dedicated PPDS, LVDS, mini-LVDS, and RSDS I/O standards are supported in row I/O banks 1, 2, 5, and 6 only.
External resistors are needed for column I/O banks.
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
The HSTL-12 Class II is supported in column I/O banks 3, 4, 7, and 8 only.
The differential SSTL-18 and SSTL-2, differential HSTL-18, and HSTL-15 I/O standards are only supported on clock
input pins and PLL output clock pins.
The differential HSTL-12 I/O standards is only supported on clock input pins and PLL output clock pins.
Differential HSTL-12 class II is only supported in column I/O banks 3, 4, 7 and 8 only.
Figure
7–14:
I/O Bank 8
I/O Bank 3
(1)
All I/O Banks Support:
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PPDS
LVDS
RSDS
mini-LVDS
LVPECL (3)
SSTL-2 class I and II
SSTL-18 CLass I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II (4)
Differential SSTL-2 (5)
Differential SSTL-18 (5)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
Differential HSTL-12 (6)
I/O Bank 4
I/O Bank 7
Cyclone III Device Handbook, Volume 1
I/O Banks
7–27