EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 159

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 7–5. Control Signal Selection Per IOE
Altera Corporation-Preliminary
March 2007
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Dedicated I/O
Clock [5..0]
The pin's datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks (
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions.
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
io_coe
In bidirectional operation, you can use the input register for input data
requiring fast setup times. The input register can have its own clock input
and clock enable separate from the OE and output registers. You can use
the output register for data requiring fast clock-to-output performance.
The OE register is available for fast clock-to-output enable timing. The OE
and output register share the same clock source and the same
clock-enable source from the local interconnect in the associated LAB,
dedicated I/O clocks, or column and row interconnects. All registers
share sclr and aclr, but each register can individually disable sclr
and aclr.
io_cce_out
io_csclr
io_cee_in
io_caclr
io_cclk
Figure 7–6
shows the IOE in bidirectional configuration.
Figure 7–5
clk_in
io_clk[5..0]
clk_out
Cyclone III Device Handbook, Volume 1
illustrates the control signal selection.
) provide a dedicated routing
ce_in
ce_out
Cyclone III I/O Element
aclr/preset
sclr/preset
7–7
oe