EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 439

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device Datasheet: DC & Switching Characteristics
Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
(4)
(5)
Note to
(1)
DDR2
SDRAM
(2)
DDR
SDRAM
(2)
QDRII
SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
Standard
Table 1–35. Cyclone III Maximum Clock Rate Support for External Memory Interfaces
Table 1–36. FPGA Sampling Window (SW) Requirement - Read Side
Memory
Standards
Memory
These numbers are preliminary until characterization is final.
The values apply for interfaces with both modules and components.
Support will be evaluated after characterization.
QDRII SRAM also supports the 1.5-V HSTL I/O standard. However, Altera recommends using the 1.8-V HSTL
I/O standard for maximum performance because of the higher I/O Current Strength.
Column I/Os refer to Top and Bottom I/Os. Row I/Os refer to Right and Left I/Os.
Column I/Os refer to Top and Bottom I/Os. Row I/Os refer to Right and Left I/Os.
(4)
Table
Table
HSTL class
1.8V HSTL
Standard
SSTL-18
SSTL-18
1–36:
SSTL-2
SSTL-2
class II
class II
class II
1–35:
class I
class I
1.8-V
I/O
Setup Hold
Column I/Os
I
620
595
695
–6 Speed Grade
Column I/Os
620
595
695
-6 Speed Grade (MHz)
Use the following tables for memory interface timing analysis..
200
133
167
133
167
100
Setup
745
730
780
Row I/Os
Row I/Os
Hold Setup
745
730
780
150
125
150
167
125
(3)
Column I/Os
755
728
790
Column I/Os
–7 Speed Grade
-7 Speed Grade (MHz)
Hold Setup
755
728
790
167
125
150
125
150
(3)
Commercial
840
843
885
Row I/Os
Row I/Os
(1)
150
133
100
133
(3)
Hold
(3)
840
843
885
Setup
Column I/Os
790
895
850
Column I/Os
-8 Speed Grade (MHz)
167
133
100
133
Cyclone III Handbook
–8 Speed Grade
(3)
(3)
(1) (5)
Hold
790
850
895
Setup
945
975
970
Row I/Os
Row I/Os
133
125
125
(3)
(3)
(3)
1–29
Hold
Preliminary
945
975
970
Units
ps
ps
ps