EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 314

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
Figure 10–26. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1)
(2)
(3)
(4)
10–78
Cyclone III Device Handbook, Volume 1
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect the nCONFIG pin to V
and DATA[0] to either high or low, whichever is convenient on your board.
nCE must be connected to GND or driven low for successful JTAG configuration.
All I/O inputs must maintain a maximum AC voltage of 4.1 V. Signals driving into TDI, TMS, and TCK has to fit the
maximum overshoot equation outlined in
Figure
10–26:
f
Microprocessor
ADDR
1
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for
in-system programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
For more information about JTAG and Jam STAPL in embedded
environments, refer to the AN 122: Using Jam STAPL for ISP and ICR via
an Embedded Processor. To download the jam player, visit the Altera web
site at www.altera.com.
Memory
DATA
All I/O inputs must maintain a maximum AC voltage of 4.1 V.
Signals driving into TDI, TMS, and TCK has to fit the maximum
overshoot equation outlined in
I/O Requirements” on page
“Configuration and JTAG Pin I/O Requirements” on page
N.C.
(2)
(2)
(2)
CC
nCONFIG
DATA[0]
DCLK
TDI (4)
TCK (4)
TMS (4)
nCEO
Cyclone III FPGA
nCE
, and the MSEL[3..0] pins to ground. In addition, pull DCLK
CONF_DONE
(3)
MSEL[3..0]
nSTATUS
TDO
10–13.
V
(2)
CCIO
“Configuration and JTAG Pin
10 kΩ
Altera Corporation-Preliminary
(1)
V
CCIO
10 kΩ
(1)
March 2007
10–13.