EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 228

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

External Memory Interfaces in Cyclone III Devices
9–14
Cyclone III Device Handbook, Volume 1
The data mask (DM) pins are only required when writing to DDR2 and
DDR SDRAM devices. QDRII SRAM devices use the BWS# signal to select
the byte to be written into memory. A low signal on the DM or BWS# pin
indicates the write is valid. Driving the DM or BWS# pin high causes the
memory to mask the DQ signals. Each group of DQS and DQ signals has
one DM pin. Similar to the DQ output signals, the DM signals are clocked by
the –90° shifted clock.
In Cyclone III devices, the DM pins are preassigned in the device pinouts.
The Quartus II fitter treats the DQ and DM pins in a DQS group equally for
placement purposes. The preassigned DQ and DM pins are the preferred
pins to use.
Some DDR2 SDRAM and DDR SDRAM devices support error correction
coding (ECC), a method of detecting and automatically correcting errors
in data transmission. In 72-bit DDR2 or DDR SDRAM, there are eight
ECC pins and 64 data pins. Connect the DDR2 and DDR SDRAM ECC
pins to a DQS/DQ group in Cyclone III devices. The memory controller
needs additional logic to encode and decode the ECC data.
Address and Control/Command Pins
The address signals and the control or command signals are typically sent
at a single data rate. You can use any of the user I/O pins on all I/O banks
of Cyclone III devices to generate the address and control or command
signals to the memory device.
1
Memory Clock Pins
In DDR2 and DDR SDRAM memory interfaces, the memory clock signals
(CK and CK#) are used to capture the address signals and the control or
command signals. Similarly, QDRII SRAM devices use the write clocks (K
and K#) to capture the address and command signals. The CK/CK# and
K/K# signals are generated to mimic the write-data strobe using the
DDIO registers in Cyclone III devices. You can use any regular adjacent
I/O pins to generate the CK/CK# for DDR2 and DDR SDRAM interface
or K/K# for QDRII SRAM.
Cyclone III devices do not support QDRII SRAM in the burst
length of two.
Altera Corporation-Preliminary
March 2007