EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 8

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Contents
Section II. I/O and External Memory Interfaces
Chapter 7. Cyclone III Device I/O Features
Chapter 8. High-Speed Differential Interfaces in Cyclone III Devices
viii
Board Layout ........................................................................................................................................ 6–47
Conclusion ............................................................................................................................................ 6–49
Document Revision History ............................................................................................................... 6–50
Introduction ............................................................................................................................................ 7–1
Overview ................................................................................................................................................. 7–1
Cyclone III
I/O Element ............................................................................................................................................ 7–2
I/O Element Features ............................................................................................................................ 7–8
On-Chip Termination Support .......................................................................................................... 7–15
I/O Standards ...................................................................................................................................... 7–20
Termination Scheme for
I/O Standards ...................................................................................................................................... 7–22
I/O Banks .............................................................................................................................................. 7–26
Pad Placement and DC Guidelines ................................................................................................... 7–32
Conclusion ............................................................................................................................................ 7–38
Document Revision History ............................................................................................................... 7–38
Introduction ............................................................................................................................................ 8–1
Cyclone III High-Speed
I/O Banks ................................................................................................................................................ 8–2
Cyclone III High-Speed
VCCA and GNDA .......................................................................................................................... 6–47
VCCD and GND ............................................................................................................................. 6–48
Programmable Current Strength ................................................................................................... 7–8
Slew Rate Control ........................................................................................................................... 7–11
Open-Drain Output ........................................................................................................................ 7–11
Bus Hold .......................................................................................................................................... 7–12
Programmable Pull-Up Resistor .................................................................................................. 7–12
Programmable Delay ..................................................................................................................... 7–13
PCI-Clamp Diode ........................................................................................................................... 7–14
LVDS Transmitter Programmable Pre-Emphasis ...................................................................... 7–14
On-Chip Termination With Calibration ...................................................................................... 7–15
On-Chip Termination Without Calibration ................................................................................ 7–17
Voltage-Referenced I/O Standard Termination ........................................................................ 7–22
Differential I/O Standard Termination ...................................................................................... 7–24
High-Speed Differential Interfaces .............................................................................................. 7–31
External Memory Interfacing ....................................................................................................... 7–32
Differential Pad Placement Guidelines ....................................................................................... 7–32
V
DC Guidelines ................................................................................................................................. 7–37
REF
Pad Placement Guidelines ................................................................................................... 7–34
Cyclone III Device Handbook, Volume 1
Altera Corporation