EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 460

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EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
Datasheets

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Typical Design Performance
1–50
Cyclone III Handbook
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V
LVTTL/LVCMOS
1.8-V
LVTTL/LVCMOS
Table 1–48. EP3C10 Column I/O Pin Input Timing Parameters for Single-Ended I/O Standards (Part 1 of 3)
I/O Standard
f
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Clock
For more information about the differential I/O interface, please refer to
High-Speed Differential Interfaces in Cyclone III Devices
Handbook.
EP3C10 I/O Timing Parameters
Table 1–48
parameters for EP3C10 devices.
Parameter
through
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
SU
SU
SU
SU
SU
SU
SU
SU
SU
SU
SU
H
H
H
H
H
H
H
H
H
H
H
H
Table 1–52
-0.826
-3.722
-0.826
-3.722
-0.826
-3.722
-0.826
-3.722
-0.836
-3.732
-0.763
-3.659
1.026
3.922
1.026
3.922
1.026
3.922
1.026
3.922
1.036
3.932
0.963
3.859
-6
show the maximum I/O timing
Specification
-0.950
-4.098
-0.950
-4.098
-0.950
-4.098
-0.950
-4.098
-0.889
-4.037
-0.846
-3.994
1.181
4.329
1.181
4.329
1.181
4.329
1.181
4.329
1.120
4.268
1.077
4.225
-7
Altera Corporation- Preliminary
-0.944
-4.381
-0.944
-4.381
-0.944
-4.381
-0.944
-4.381
-0.881
-4.318
-0.869
-4.306
1.207
4.644
1.207
4.644
1.207
4.644
1.207
4.644
1.144
4.581
1.132
4.569
of the Cyclone III
-8
March 2007
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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