EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 144

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
6–44
Cyclone III Device Handbook, Volume 1
Note to
(1)
PLL Scan Chain Bits [0..8] Settings
LSB
Table 6–13. PLL Counter Settings
X
X
Bypass bit.
X
X
Table
X
X
6–13:
X
X
X
X
Bypassing PLL Counter
Bypassing a PLL counter results in a multiply (m counter) or a divide
(n, C0 to C4 counters) factor of one.
Table 6–13
PLLs.
To bypass any of the PLL counters, set the bypass bit to 1. This ignores the
values on the other bits.
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual
PLL outputs to be dynamically adjusted relative to each other and the
reference clock without the need to send serial data through the scan
chain of the corresponding PLL. This simplifies the interface and allows
you to quickly adjust clock-to-out (tco) delays by changing output clock
phase shift in real time. This is achieved by incrementing or decrementing
the VCO phase-tap selection to a given C counter or to the M counter. The
phase is shifted by 1/8 the VCO frequency at a time. The output clocks
are active during this phase reconfiguration process.
X
X
X
X
shows the settings for bypassing the counters in Cyclone III
X
X
MSB
1
0
(1)
(1)
PLL counter bypassed
PLL counter not bypassed
Description
Altera Corporation- Preliminary
March 2007