EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 208

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

High-Speed Differential Interfaces in Cyclone III Devices
Figure 8–18. Differential SSTL Class I Interface
Figure 8–19. Differential SSTL Class II Interface
8–18
Cyclone III Device Handbook, Volume 1
Output Buffer
Output Buffer
25 Ω
25 Ω
25 Ω
25 Ω
Figures 8–18
respectively.
Differential HSTL I/O Standard Support in Cyclone III Devices
The differential HSTL I/O standard is used for the applications designed
to operate in the 0 V to 1.2 V, 0 V to 1.5 V, or 0 V to 1.8 V HSTL logic
switching range. Cyclone III devices support differential HSTL-18, HSTL-
15, and HSTL-12 I/O standards. The differential HSTL AC and DC
specifications are the same as the HSTL single-ended specifications. The
differential HSTL input standard is available on the GCLK pins only,
treating differential inputs as two single-ended HSTL and only decoding
one of them. The differential HSTL output standard is only supported at
the PLL#_CLKOUT pins using two single-ended HSTL output buffers
(PLL#_CLKOUTp and PLL#_CLKOUTn), with the second output
programmed as inverted. The standard requires two differential inputs
with an external reference voltage (V
termination voltage (V
connected.
V
TT
50 Ω
and
V
TT
8–19
50 Ω
Z 0 = 50 Ω
Z 0 = 50 Ω
Z 0 = 50 Ω
Z 0 = 50 Ω
TT
show the differential SSTL class I and II interfaces,
) of 0.5 x V
V
V
TT
TT
50 Ω
50 Ω
CCIO
REF
to which termination resistors are
), as well as an external
V
V
TT
TT
Altera Corporation-Preliminary
50 Ω
50 Ω
Receiver
Receiver
March 2007