EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 192

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

High-Speed Differential Interfaces in Cyclone III Devices
Cyclone III
High-Speed
I/O Banks
8–2
Cyclone III Device Handbook, Volume 1
f
professional LCD monitor. Cyclone III devices support the PPDS I/O
standards at speed up to 440 Mbps with no external resistors required at
the dedicated transmitter located on the left and right I/O banks.
The differential interface data serializers and deserializers (SERDES) are
constructed automatically in Cyclone III logic elements with Quartus
software altlvds megafunction.
This chapter describes how to use Cyclone III I/O pins for differential
signaling and contains the following topics:
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Cyclone III device I/Os are separated into eight I/O banks, as shown in
Figure
output drivers for LVDS, RSDS, mini-LVDS, and PPDS are on the left and
right I/O banks. These I/O standards are also supported on the top and
bottom I/O banks using external resistors. On the left and right I/O
banks, some of the differential pin pairs (p and n pins) of the dedicated
output drivers are not located on adjacent pins. In these cases, a power
pin is located between the p and n pins.
Refer to the pin tables on the Altera web site at www.altera.com for more
details on the location of the dedicated differential pins.
Table 8–1
standards.
Cyclone III high-speed I/O banks
Cyclone III high-speed I/O interface
High-speed I/O standards support
High-speed I/O timing in Cyclone III devices
Design guidelines
Software Overview
8–1. Each bank has an independent power supply. Dedicated
shows the performance target for various differential I/O
Altera Corporation-Preliminary
March 2007
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II