EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 285

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
dialog box. Supplying a clock on CLKUSR does not affect the
configuration process. After all the configuration data is accepted and
CONF_DONE goes high, CLKUSR is enabled after the time specified as
t
clock cycles to initialize properly and enter user mode. Cyclone III
devices support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If you use the INIT_DONE pin, it will be high due to an external 10 KΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. The MAX II device must be
able to detect this low-to-high transition which signals the device has
entered user mode. When initialization is complete, the device enters user
mode. In user mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DCLK and DATA[0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[0] pin is available as
a user I/O pin after configuration. When you choose the PS scheme in the
Quartus II software, the DATA[0] pin is tri-stated, by default, in user
mode and should be driven by the MAX II device. To change this default
option in the Quartus II software, select the Dual-Purpose Pins tab of the
Device & Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified system
frequency to ensure correct configuration (refer to
page
pause configuration by halting DCLK for an indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box) is turned
on, the Cyclone III device releases nSTATUS after a reset time-out period
(maximum of 80 µs). After nSTATUS is released and pulled high by a pull-
up resistor, the MAX II device can try to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 500 ns) on nCONFIG to restart the configuration process.
CD2CU
10–54). No maximum DCLK period exists, which means you can
. After this time period elapses, Cyclone III devices require 3,180
MAX
of 133 MHz.
Cyclone III Device Handbook, Volume 1
Passive Serial Configuration
Table 10–11 on
10–49