EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 189

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
After applying the equation above, apply one of the equations in
Table
Each I/O bank can only be set to a single V
V
share the bank if they have compatible V
voltage levels (refer to
DDR/DDR2 and QDRII Pads
For dedicated DQ and DQS pads on a DDR interface, DQ pads must be on
the same power bank as DQS pads. With the DDR and DDR2 memory
interfaces, a V
No other I/O can be placed within the same power bank where DQ pins
are located, except DDR/DDR2 usage pins.
For a QDRII interface, D is the QDRII output and Q is the QDRII input.
D pads and Q pads must be on the same power bank as CQ. With the QDR
and QDRII memory interfaces, a V
maximum of five D and Q pads. No other I/O can be placed within the
same power bank where D or Q pins located. Besides, the D, cms, and
address pads can not be placed at the same V
located.
By default, the Quartus II software assigns D and Q pads as regular I/O
pins. If you do not specify the function of a D or Q pad in the Quartus II
software, the software sets them as regular I/O pins. If this occurs,
Cyclone III QDR and QDRII performance is not guaranteed.
DC Guidelines
There is a current limit of 240 mA per twelve consecutive output top and
bottom pins per power pair, as shown by the following equation:
pin+11
FineLine BGA
QFP
Table 7–12. Bidirectional Pad Limitation Formulas (Multiple V
Outputs)
REF
Package Type
voltage level at a given time. Pins of different I/O standards can
7–12, depending on the package type.
CCIO
and ground pair can have a maximum of five DQ pads.
(Total number of bidirectional pads) + (Total number of
output pads) ≤ 9 (per
Total number of bidirectional pads + Total number of output
pads ≤ 5 (per
Table 7–7
V
CCIO
for more details).
CCIO
Cyclone III Device Handbook, Volume 1
/
GND
V
and ground pair can have a
CCIO
Pad Placement and DC Guidelines
CCIO
pair)
Formula
/
CCIO
GND
values and compatible V
REF
voltage level and a single
pair)
bank where Q pads are
REF
Inputs and
7–37
REF