EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 68

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Memory Blocks in Cyclone III Devices
4–14
Cyclone III Device Handbook, Volume 1
Read Port
8192 × 1
4096 × 2
2048 × 4
1024 × 8
512 × 16
1024 × 9
512 × 18
Table 4–5. Cyclone III M9K Block Mixed-Width Configurations (True Dual-Port Mode)
8192 × 1
v
v
v
v
v
Figure 4–11. Cyclone III True Dual-Port Memory
Note to
(1)
1
Table 4–5
In true dual-port mode, M9K memory blocks support separate
write-enable and read-enable signals. You can save power by keeping the
read-enable signal low (inactive) when not reading. Read-during-write
operations to the same address can either output “New Data” at that
location or “Old Data”. To choose the desired behavior, set the
Read-During-Write option to either “New Data” or “Old Data” in the
RAM MegaWizard in the Quartus II software. See
Operations” on page 4–28
4096 × 2
True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
v
v
v
v
v
Figure
The widest bit configuration of the M9K blocks in true dual-port
mode is 512 × 16-bit (18-bit with parity).
lists the possible M9K block mixed-port width configurations.
4–11:
2048 × 4
v
v
v
v
v
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clocken_a
rden_a
aclr_a
q_a[]
clock_a
Write Port
1024 × 8
for more details on this behavior.
v
v
v
v
v
512 × 16
addressstall_b
v
v
v
v
v
address_b[]
byteena_b[]
Altera Corporation-Preliminary
clocken_b
(1)
data_b[ ]
clock_b
wren_b
rden_b
aclr_b
q_b[]
1024 × 9
“Read-During-Write
v
v
512 × 18
March 2007
v
v