EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 196

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

High-Speed Differential Interfaces in Cyclone III Devices
High-Speed
I/O Standards
Support
8–6
Cyclone III Device Handbook, Volume 1
Notes to
(1)
(2)
EP3C120
Table 8–2. Cyclone III Device Differential Channels (Part 2 of 2) (1),
User I/O pins can be used as inputs or outputs; clock input pins can be used as inputs only.
The pin count figures are preliminary.
Device
Table
8–2:
f
Package
FBGA
FBGA
This section provides information on the high-speed I/O standards that
Cyclone III devices support.
LVDS I/O Standard Support in Cyclone III Devices
The LVDS I/O standard is a high-speed, low-voltage swing, low power,
and general purpose I/O interface standard. The Cyclone III device meets
the ANSI/TIA/EIA-644 standard with the following exceptions:
■
■
See the Cyclone III Device Datasheet: DC and Switching Characteristics of
Cyclone III Devices chapter in volume 2 of the Cyclone III Device Handbook
for the LVDS I/O standard electrical specifications.
All the Cyclone III device I/O banks support LVDS channels. The left and
right I/O banks support dedicated LVDS transmitters. On the top and
bottom I/O banks, the LVDS transmitters are supported using external
resistors. The LVDS standard does not require an input reference voltage;
however, it does require an external 100-Ω termination resistor between
the two signals at the input buffer.
LVDS Transmitter
Cyclone III LVDS dedicated transmitters, which are located on the left
and right I/O banks, support a data rate up to 840 Mbps, and the
transmitters located on the top and bottom I/O banks support up to
640 Mbps (using external resistors).
The maximum voltage output differential (VOD) is increased to
600 mV. The maximum VOD for ANSI specification is 450 mV.
The input voltage range can be reduced to the range of 1.0 V to 1.6 V,
0.5 V to 1.85 V or 0 V to 1.8 V based on different frequency ranges.
The ANSI/TIA/EIA-644 specification supports an input voltage
range of 0 V to 2.4 V.
Pin Count
484
780
User I/O
221
94
(2)
Number of Differential Channels
Altera Corporation-Preliminary
Clock Pin
8
8
March 2007
Total
102
229