EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 280

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
10–44
Cyclone III Device Handbook, Volume 1
f
1/16 that of the AS configuration time. Therefore, the maximum
configuration time estimate for an EP3C10 device (3,500,000 bits of
uncompressed data) is:
RBF Size × (maximum DCLK period / 16 bit per DCLK cycle) = estimated
maximum configuration time
3,500,000 bits × (50 ns / 16 bit) = 10.9 ms
To estimate the typical configuration time, use the typical DCLK period as
listed in
the typical configuration time is 7.3 ms.
Programming Parallel Flash Memories
The supported parallel flash memories are external non-volatile
configuration devices. They are industry standard microprocessor flash
memories.
For information on the supported families for the commodity parallel
flash, refer to
Cyclone III devices in a single device chain or in a multiple device chain
support in-system programming of a parallel flash using the JTAG
interface via the flash loader megafunction. The board’s intelligent host
or download cable can use the four JTAG pins on the Cyclone III device
to program the parallel flash in system, even if the host or download cable
cannot access the parallel flash’s configuration pins.
1
In the AP configuration scheme, the default configuration boot address is
0×010000 in the supported parallel flash memory. This allows special
parameter blocks within the flash memory map to be used by the system.
The parameter blocks can be at the top or bottom of the memory map. The
configuration boot address in the AP configuration scheme is shown in
Figure
address to any desired address using the JTAG instruction
APFC_BOOT_ADDR.
10–13. You can change the default configuration default boot
Table 10–7 on page
The flash loader design supporting AP flash programming is a
new megafunction in Quartus II software. Please contact Altera
Technical Support for more information on the new
megafunction.
Table 10–9 on page
10–17. With a typical DCLK period of 33.33ns,
10–32.
Altera Corporation-Preliminary
March 2007