EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 9

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Contents
Chapter 9. External Memory Interfaces in Cyclone III Devices
Section III. Configuration, Hot Socketing, Remote Upgrades, and SEU
Mitigation
Chapter 10. Configuring Cyclone III Devices
Altera Corporation
I/O Interface ........................................................................................................................................... 8–5
High-Speed
I/O Standards Support ......................................................................................................................... 8–6
High-Speed
I/O Timing in Cyclone III Devices .................................................................................................... 8–20
Design Guidelines ............................................................................................................................... 8–22
Software Overview .............................................................................................................................. 8–23
Conclusion ............................................................................................................................................ 8–24
Document Revision History ............................................................................................................... 8–24
Introduction ............................................................................................................................................ 9–1
Cyclone III Memory Support Overview ............................................................................................ 9–3
Cyclone III Memory Interfaces Pin Support ...................................................................................... 9–5
Cyclone III Memory Interfaces Features .......................................................................................... 9–15
Conclusion ............................................................................................................................................ 9–19
Document Revision History ............................................................................................................... 9–19
Introduction .......................................................................................................................................... 10–1
LVDS I/O Standard Support in Cyclone III Devices .................................................................. 8–6
RSDS I/O Standard Support in Cyclone III Devices ................................................................... 8–9
mini-LVDS I/O Standard Support in Cyclone III Devices ...................................................... 8–12
PPDS I/O Standard Support in Cyclone III Devices ................................................................ 8–14
LVPECL I/O Support in Cyclone III Devices ............................................................................ 8–16
Differential SSTL I/O Standard Support in Cyclone III Devices ............................................ 8–17
Differential HSTL I/O Standard Support in Cyclone III Devices ........................................... 8–18
Feature of the Dedicated Output Buffer ..................................................................................... 8–19
Differential Pad Placement Guidelines ....................................................................................... 8–22
Board Design Considerations ....................................................................................................... 8–22
Data and Data Clock/Strobe Pins .................................................................................................. 9–6
Optional Parity, DM, and ECC Pins ............................................................................................ 9–13
Address and Control/Command Pins ........................................................................................ 9–14
Memory Clock Pins ........................................................................................................................ 9–14
DDR Input Registers ...................................................................................................................... 9–15
DDR Output Registers ................................................................................................................... 9–16
On-Chip Termination (OCT) ........................................................................................................ 9–18
PLL ................................................................................................................................................... 9–18
Configuration Devices ................................................................................................................... 10–2
Configuration Schemes ................................................................................................................. 10–2
Configuration File Format ............................................................................................................ 10–7
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