EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 136
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Clock Networks and PLLs in Cyclone III Devices
Figure 6–21. PLL Cascading Using GCLK
Note to
(1)
6–36
Cyclone III Device Handbook, Volume 1
Output from PLL
Control Blocks
Five Clock
For the EP3C5 and EP3C10 devices, there are only two PLLs (PLL1 and PLL2), ten clock control blocks and ten
GCLKs.
from Two Clock
edge of device
pin at adjacent
Remote clock
Figure
CLK[0..3]
6–21:
2
PLL
PLL
2
3
1
5
1
Output from PLL
GCLK[0..4]
20
GCLK[0:19]
Input to PLL
5
2
2
GCLK[15..19]
Note (1)
Control Blocks
GCLK[0:19]
Five Clock
CLK[8..11]
CLK[12..15]
1
20
4
GCLK[10..14]
20
1
Control Blocks
Five Clock
GCLK[0:19]
2
2
Output from PLL
GCLK[5..9]
5
20
Altera Corporation- Preliminary
1
PLL
PLL
2
5
4
2
2
CLK[4..7]
4
Output from PLL
Five Clock
Control Blocks
March 2007
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