EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 443

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device Datasheet: DC & Switching Characteristics
Figure 1–2. Output Register Clock to Output Timing Diagram
Altera Corporation-Preliminary
March 2007
Clock pad to output Register delay
Clock
Datain
The following measurements are made during device characterization.
Altera measures clock-to-output delays (
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in
clock pin to output pin timing for Cyclone III devices.
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
2.
3.
4.
5.
t
register + IOE output register clock-to-output delay + delay from
output register to output pin
Simulate the output driver of choice into the generalized test setup,
using values from
Record the time to V
Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
CO
from clock pin to I/O pin = delay from clock pad to I/O output
Output Register
micro t CO
Table
Table
MEAS
MEAS
1–41. Use the following equations to calculate
1–41.
.
.
Output Register to output pin delay
t
CO
) at worst-case process,
Cyclone III Handbook
output
1–33