EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 55

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Introduction
Overview
Altera Corporation-Preliminary
March 2007
CIII51005-1.0
Cyclone
on-chip memory needs of Altera
embedded memory structure consists of columns of M9K memory blocks
that you can configure to provide various memory functions, such as
RAM, shift registers, ROM, and first-in first-out (FIFO) buffers. M9K
memory blocks provide up to 3.98 Mbit of RAM at a maximum of
260 MHz for synchronous operation (see
bits-per-density).
The M9K blocks support the following features:
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Table 4–1
Maximum performance
Total RAM bits (including parity bits)
Table 4–1. Summary of M9K Memory Features (Part 1 of 2)
Up to 3.98 Mbit of RAM available without reducing available logic
8,192 memory bits per block (9,216 bits per block including parity)
Independent read-enable and write-enable signals for each port
Packed mode in which the M9K memory block is split into two 4.5 K
single-port RAMs
Variable port configurations
Single-port and simple dual-port modes support for all port widths
True dual-port (one read and one write, two reads, or two writes)
operation
Byte enables for data input masking during writes
Two clock-enable control signals for each port (port A and port B)
Initialization file to pre-load content of memory in RAM and ROM
modes
Up to 260 MHz for synchronous only operation
®
III devices feature embedded memory structures to address the
summarizes the features supported by the M9K memory.
Feature
®
4. Memory Blocks in
Cyclone III device designs. The
Cyclone III Devices
Table 4–2
M9K Blocks
260 MHz
for total RAM
9,216
4–1