EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 446

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

I/O Timing
1–36
Cyclone III Handbook
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
LVDS
LVDS_E_3R
mini-LVDS
mini-LVDS_E_3R
PPDS
PPDS_E_3R
RSDS
RSDS_E_1R
RSDS_E_3R
Table 1–41. Output Timing Measurement Methodology for Output Pins (1), (2), (4),
2 of 2)
Input measurement point at internal node is 0.5 x V
Output measuring point for V
Input stimulus edge rate is 0 to V
Less than 50-mV ripple on V
The interface has to use external termination RT. The termination voltage V
power supply or created through a Thevenin equivalent circuit.
Pending silicon characterization.
I/O Standard
Table
1–41:
120
120
120
120
R
S
(Ω)
(6)
(6)
(6)
(6)
I/O Default Capacitive Loading
See
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
Table 1–42. Default Loading of Different I/O Standards for
Cyclone III (Part 1 of 2)
CCIO
MEAS
Table 1–42
. V
R
CC
T
at buffer output is 0.5 x V
CCINT
in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
(Ω)
I/O Standard
=1.10 V with less than 30-mV ripple.
R
for default capacitive loading of different I/O standards.
100
100
100
100
100
100
100
100
100
D
Loading and Termination
(Ω)
CCINT
170
170
170
100
170
R
P
.
(Ω)
(6)
(6)
(6)
(6)
(6)
CCIO
.
V
CCIO
2.375
2.375
2.375
2.375
2.375
2.375
2.375
2.375
2.375
(V)
Capacitive Load
TT
may either be supplied by an independent
Altera Corporation- Preliminary
V
TT
0
0
0
0
0
0
0
0
(V)
(5)
C
L
(Part
(pF)
0
0
0
0
0
0
0
0
0
Preliminary
March 2007
Unit
Measurement
pF
pF
pF
pF
pF
pF
pF
pF
Preliminary
V
1.1875
1.1875
1.1875
1.1875
1.1875
1.1875
1.1875
1.1875
1.1875
MEAS
Point
(V)