EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 394

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
Using IEEE Std.
1149.1 BST
Circuitry
14–20
Cyclone III Device Handbook, Volume 1
Figure 14–13. JTAG Chain of Mixed Voltages
Cyclone III devices have dedicated JTAG pins and the IEEE Std. 1149.1
BST circuitry is enabled upon device power-up. Not only can you
perform BST on Cyclone III FPGAs before and after, but also during
configuration. Cyclone III FPGAs support the BYPASS, IDCODE and
SAMPLE instructions during configuration without interrupting
configuration. To send all other JTAG instructions, you must interrupt
configuration using the CONFIG_IO instruction except for active
configuration schemes where ACTIVE_DISENGAGE instruction is used
instead.
The CONFIG_IO instruction allows you to configure I/O buffers via the
JTAG port, and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Cyclone III FPGA or you can wait for the configuration device to
complete configuration. Once configuration is interrupted and JTAG BST
is complete, you must reconfigure the part via JTAG (PULSE_NCONFIG
instruction) or by pulsing nCONFIG low.
1
When you design a board for JTAG configuration of Cyclone III devices,
you need to consider the connections for the dedicated configuration
pins.
Tester
When you perform JTAG boundary-scan testing before
configuration, the nCONFIG pin must be held low.
TDO
TDI
tester if necessary
level accepted by
Shift TDO to
Shifter
Level
V
3.3 V
CCIO
Must be
tolerant
V
1.5 V
1.8 V
CCIO
Altera Corporation-Preliminary
Must be
tolerant
V
2.5 V
3.3 V
CCIO
Must be
tolerant
V
1.8 V
2.5 V
CCIO
March 2007