EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 92

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EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Embedded Multipliers in Cyclone III Devices
Architecture
5–4
Cyclone III Device Handbook, Volume 1
f
f
Refer to the Cyclone III Memory Blocks chapter in volume 1 of the
Cyclone III Device Handbook for more information on Cyclone III M9K
memory blocks.
Refer to AN 306: Techniques for Implementing Multipliers in FPGA Devices
for more information about soft multipliers.
Each embedded multiplier consists of the following elements:
Figure 5–2
Notes to
(1)
(2)
EP3C55
EP3C80
Table 5–2. Number of Multipliers in Cyclone III Devices (Part 2 of 2)
Device
Multiplier stage
Input and output registers
Input and output interfaces
Soft multipliers are implemented in sum of multiplication mode. The M9K
memory blocks are configured with 18-bit data widths to support 16-bit
coefficients. The sum of the coefficients requires 18-bits of resolution to account
for overflow.
The total number of multipliers may vary according to the multiplier mode you
use.
Table
shows the multiplier block architecture.
5–2:
Multipliers (18 × 18)
Embedded
156
244
Soft Multipliers
(16 × 16)
Altera Corporation-Preliminary
260
305
(1)
Total Multipliers
March 2007
416
549
(2)

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