EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 56

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Memory Blocks in Cyclone III Devices
4–2
Cyclone III Device Handbook, Volume 1
Notes to
(1)
(2)
Configurations (depth x width)
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
Embedded shift register mode
ROM mode
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register asynchronous clears
Latch asynchronous clears
Write/Read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Table 4–1. Summary of M9K Memory Features (Part 2 of 2)
FIFO buffers and embedded shift registers that require external logic elements
(LEs) for implementing control logic.
Width modes of × 32 and × 36 are not available.
Table
(1)
4–1:
(1)
(2)
Outputs cleared
Read address registers and output
registers only
Output latches only
Write and Read: Rising clock edges
Outputs set to “Old Data” or “New Data”
Outputs set to “Old Data” or “Don’t
Care”
Altera Corporation-Preliminary
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
v
v
v
v
v
v
v
v
v
v
v
v
v
v
March 2007