NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 115

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.2.2.4
5.2.3
Figure 6.
5.2.4
5.2.4.1
Intel
®
ICH8 Family Datasheet
SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating
systems. To support power management on non-PCI Express aware operating systems,
PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.
When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/
F5:Offset DCh:bit 31) to be set.
Additionally, BIOS workarounds for power management can be supported by setting
MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power
management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0),
and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI
is enabled. The SMI# may occur concurrently with an interrupt or SCI.
SERR# Generation
SERR# may be generated via two paths – through PCI mechanisms involving bits in the
PCI header, or through PCI Express mechanisms involving bits in the PCI Express
capability structure.
Generation of SERR# to Platform
Hot-Plug
Each root port implements a Hot-Plug controller which performs the following:
The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Edge-connector
based Hot-Plug is not supported.
Presence Detection
When a module is plugged in and power is supplied, the physical layer will detect the
presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/
F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE
(D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3F4/
F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt.
When a module is removed (via the physical layer detection), the root port clears
SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root
port will also generate an interrupt.
• Messages to turn on / off / blink LEDs
• Presence and attention button detection
• Interrupt generation
PCI
PCI Express
Secondary Parity Error
Primary Parity Error
Secondary SERR#
Correctable SERR#
Non-Fatal SERR#
Fatal SERR#
PCICMD.SEE
PSTS.SSE
SERR#
115