NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 620

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

15.2.3
Table 136.
620
USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base
Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the
debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register
at Configuration offset 5Ah (D29:F7, D26:F7:offset 5Ah). The specific EHCI port that
supports this debug capability (Port 0 for D29:F7 and Port 6 for D26:F7) is indicated by
a 4-bit field (bits 20–23) in the HCSPARAMS register of the EHCI controller. The address
map of the Debug Port registers is shown in
Debug Port Register Address Map
NOTES:
1.
2.
MEM_BASE +
Bit
2
1
0
A0–A3h
A4–A7h
A8–ABh
AC–AFh
B0–B3h
Offset
The hardware associated with this register provides no checks to ensure that software
programs the interface correctly. How the hardware behaves when programmed invalidlly
is undefined.
All of these registers are implemented in the core well and reset by PLTRST#, EHC
HCRESET, and a EHC D3-to-D0 transition.
Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a
part of the reset and enable. Software cannot enable a port by writing a 1 to this bit.
Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by host software. Note that the bit status does not change until the port
state actually changes. There may be a delay in disabling or enabling a port due to
other host controller and bus events.
0 = Disable
1 = Enable (Default)
Connect Status Change — R/WC. This bit indicates a change has occurred in the
port’s Current Connect Status. Software sets this bit to 0 by writing a 1 to it.
0 = No change (Default).
1 = Change in Current Connect Status. The host controller sets this bit for all changes
Current Connect Status — RO. This value reflects the current state of the port, and
may not correspond directly to the event that caused the Connect Status Change bit
(Bit 1) to be set.
0 = No device is present. (Default)
1 = Device is present on port.
to the port device connect status, even if system software has not cleared an
existing connect status change. For example, the insertion status changes twice
before system software has cleared the changed condition, hub hardware will be
“setting” an already-set bit (i.e., the bit will remain set).
DATABUF[3:0]
DATABUF[7:4]
Mnemonic
CNTL_STS
CONFIG
USBPID
Data Buffer (Bytes 3:0)
Data Buffer (Bytes 7:4)
Control/Status
USB PIDs
Configuration
Register Name
Description
Table
EHCI Controller Registers (D29:F7, D26:F7)
136.
Intel
00000000h
00000000h R/W, RO
00000000h R/W
00000000h R/W
00007F01h R/W
Default
®
ICH8 Family Datasheet
R/W, R/WC,
RO, WO
Type