NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 646

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

17.1.3
646
PCICMD—PCI Command Register
(Intel
Offset Address: 04h
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
®
Reserved
Interrupt Disable (ID) — R/W.
0 = The INTx# signals may be asserted.
1 = The Intel
Note that this bit does not affect the generation of MSIs.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the ICH8 Intel High
Definition Audio Controller.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to
0.
Special Cycle Enable (SCE). Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. This bit controls standard PCI Express* bus
mastering capabilities for Memory and I/O, reads and writes. Note that this bit also
controls MSI generation since MSIs are essentially Memory writes.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — R/W. This bit enables memory space addresses to
the Intel High Definition Audio controller.
0 = Disable
1 = Enable
I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio
controller does not implement I/O space.
High Definition Audio Controller—D27:F0)
0000h
–
®
05h
High Definition Audio controller’s INTx# signal will be de-asserted
Intel
®
High Definition Audio Controller Registers (D27:F0)
Description
Attribute:
Size:
R/W, RO
16 bits
Intel
®
ICH8 Family Datasheet