NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 485
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 485 of 890
- Download datasheet (7Mb)
SATA Controller Registers (D31:F2)
12.1.31
Note:
12.1.32
Note:
Intel
®
ICH8 Family Datasheet
MSIMA— Message Signaled Interrupt Message Address
(SATA–D31:F2)
Address Offset: 84h
Default Value:
There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
MSIMD—Message Signaled Interrupt Message Data
(SATA–D31:F2)
Address Offset: 88h-89h
Default Value:
There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
31:2
15:0
Bits
Bits
1:0
Address (ADDR): Lower 32 bits of the system specified message address, always
DWORD aligned.
Reserved
Data (DATA)— R/W: This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven onto the lower word of the data bus of the MSI memory
write transaction. Note that when the MME field is set to ‘001’ or ‘010’, bit [0] and bits
[1:0] respectively of the MSI memory write transaction will be driven based on the
source of the interrupt rather than from MD[2:0]. See the description of the MME field.
00000000h
0000h
–
87h
Description
Description
Attribute:
Size:
Attribute:
Size:
RO, R/W
32 bits
R/W
16 bits
485
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