NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 338

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

9.1.26
9.1.27
338
FWH_SEL2—Firmware Hub Select 2 Register
(LPC I/F—D31:F0)
Offset Address: D4h
Default Value:
FWH_DEC_EN1—Firmware Hub Decode Enable Register
(LPC I/F—D31:F0)
Offset Address: D8h
Default Value:
15:12
11:8
7:4
3:0
Bit
Bit
15
14
13
FWH_70_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
FWH_60_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FWH_50_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FWH_40_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory
ranges, and one 128-KB memory range.
0 = Disable
1 = Enable the following ranges for the Firmware Hub
FWH_F0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FWH_E8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFF80000h – FFFFFFFFh
FFB80000h – FFBFFFFFh
FFF00000h – FFF7FFFFh
FFB00000h – FFB7FFFFh
FFE80000h – FFEFFFFh
FFA80000h – FFAFFFFFh
4567h
FFCFh
–
–
D5h
D9h
Description
Description
Attribute:
Size:
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
16 bits
R/W, RO
16 bits
Intel
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ICH8 Family Datasheet