NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 323

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9
9.1
Note:
.
Table 105.
Intel
®
ICH8 Family Datasheet
LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the ICH8 resides in PCI Device 31:Function 0. This function
contains many other functional units, such as DMA and Interrupt controllers, Timers,
Power Management, System Management, GPIO, RTC, and LPC Configuration
Registers.
Registers and functions associated with other functional units (EHCI, UHCI, IDE (Mobile
only), etc.) are described in their respective sections.
PCI Configuration Registers (LPC I/F—D31:F0)
Address locations that are not shown should be treated as Reserved.
LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
00h–01h
02h–03h
04h–05h
06h–07h
2Ch–2Fh
40h–43h
48h–4Bh
60h–63h
68h–6Bh
82h–83h
84h–87h
88h–8Bh
8Ch–8Eh
Offset
0Ah
0Bh
0Dh
08h
09h
0Eh
44h
64h
80h
4C
PIRQ[n]_ROUT
PIRQ[n]_ROUT
LPC_I/O_DEC
SIRQ_CNTL
Mnemonic
ACPI_CNTL
GEN1_DEC
GEN2_DEC
GEN3_DEC
GPIOBASE
HEADTYP
PMBASE
PCICMD
LPC_EN
PCISTS
SCC
BCC
VID
DID
RID
PLT
GC
SS
PI
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Primary Latency Timer
Header Type
Sub System Identifiers
ACPI Base Address
ACPI Control
GPIO Base Address
GPIO Control
PIRQ[A–D] Routing Control
Serial IRQ Control
PIRQ[E–H] Routing Control
I/O Decode Ranges
LPC I/F Enables
LPC I/F Generic Decode Range 1
LPC I/F Generic Decode Range 2
LPC I/F Generic Decode Range 3
Register Name
See register
See register
00000000h
00000001h
00000001h
00000000h
00000000h
00000000h
description
description
Default
8086h
0007h
0200h
0000h
0000h
00h
01h
06h
00h
80h
00h
00h
80h
10h
80h
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/WO
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
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