NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 293

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NH82801HEM S LA5R

Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LA5R

Lead Free Status / RoHS Status
Compliant
Chipset Configuration Registers
7.1.60
7.1.61
Intel
®
ICH8 Family Datasheet
D30IR—Device 30 Interrupt Route Register
Offset Address: 3142–3143h
Default Value:
D29IR—Device 29 Interrupt Route Register
Offset Address: 3144–3145h
Default Value:
14:12
15:0
10:8
2:0
Bit
Bit
Bit
15
11
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH8 is connected to the INTA# pin reported for device 31 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Reserved. No interrupts generated from Device 30
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Reserved
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH8 is connected to the INTC# pin reported for device 29 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
®
ICH8 is connected to the INTD# pin reported for device 29 functions.
0000h
3210h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
16-bit
R/W
16-bit
293

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