NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 692

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

17.2.40
17.2.41
692
SDLVI—Stream Descriptor Last Valid Index Register
(Intel
Memory Address:Input Stream[0]: HDBAR + 8Ch
Default Value:
SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel
Memory Address:Input Stream[0]: HDBAR + 8Eh
Default Value:
15:8
15:3
7:0
2:0
Bit
Bit
Reserved.
Last Valid Index — R/W. The value written to this register indicates the index for the
last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it
will wrap back to the first descriptor in the list and continue processing.
This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer
descriptor list before DMA operations can begin).
This value should only modified when the RUN bit is 0.
Reserved.
FIFO Watermark (FIFOW) — R/W. This field indicates the minimum number of bytes
accumulated/free in the FIFO before the controller will start a fetch/eviction of data.
010 = 8B
011 = 16B
100 = 32B (Default)
Others = Unsupported
NOTES:
1.
2.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
When the bit field is programmed to an unsupported size, the hardware sets
itself to the default value.
Software must read the bit field to test if the value is supported after setting the
bit field.
Input Stream[1]: HDBAR + ACh
Input Stream[2]: HDBAR + CCh
Input Stream[3]: HDBAR + ECh
Output Stream[0]: HDBAR + 10Ch
Output Stream[1]: HDBAR + 12Ch
Output Stream[2]: HDBAR + 14Ch
Output Stream[3]: HDBAR + 16Ch
0000h
Input Stream[1]: HDBAR + AEh
Input Stream[2]: HDBAR + CEh
Input Stream[3]: HDBAR + EEh
Output Stream[0]: HDBAR + 10Eh
Output Stream[1]: HDBAR + 12Eh
Output Stream[2]: HDBAR + 14Eh
Output Stream[3]: HDBAR + 16Eh
0004h
Intel
®
Description
Description
High Definition Audio Controller Registers (D27:F0)
Attribute:
Attribute:
Size:
Size:
Intel
®
16 bits
R/W
R/W
16 bits
ICH8 Family Datasheet