NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 292

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

7.1.58
7.1.59
292
D25IP—Device 25 Interrupt Pin Register
Offset Address: 3118–3121h
Default Value:
D31IR—Device 31 Interrupt Route Register
Offset Address: 3140–3141h
Default Value:
14:12
31:4
10:8
3:0
7:4
Bit
Bit
15
11
3
Reserved
IGBE LAN Pin (LIP): This field indicates which pin the internal GbE LAN controller
drives as its interrupt
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Reserved
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH8 is connected to the INTC# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Reserved
NetDetect Enable (NDE)— R/W. This register is in the RTC well instead of the SUS
well to maintain state if the SUS well power is removed in S4.
0 = Disabled
1 = GPIO14 input signal is multiplexed onto the South MLink MLCLK pin as a
NetDetect Request signal to the wireless LAN component.
®
ICH8 is connected to the INTD# pin reported for device 31 functions.
00000001h
3210h
Description
Description
Attribute:
Size:
Size:
Attribute:
Chipset Configuration Registers
RO, R/W
32-bit
R/W
16-bit
Intel
®
ICH8 Family Datasheet