NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 470

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

12.1.6.3
12.1.7
12.1.8
470
When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h
Address Offset: 09h
Default Value:
SCC—Sub Class Code Register (SATA–D31:F2)
Address Offset: 0Ah
Default Value:
BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2)
Address Offset: 0Bh
Default Value:
7:0
7:0
7:0
Bit
Bit
Bit
Interface (IF) — RO.
Indicates the SATA Controller supports AHCI, rev 1.1.
Sub Class Code (SCC) — RO. This field specifies the sub-class code of the controller,
per the table below:
Intel
ICH8M Only:
(Intel
Base Class Code (BCC) — RO.
01h = Mass storage device
MAP.SMS (D31:F2:Offset
MAP.SMS (D31:F2:Offset
SCC Register Attribute
®
®
ICH8 Only:
ICH8R, ICH8DH, ICH8DO, and ICH8M-E Only):
01h
See bit description
90h:bit 7:6)
90h:bit 7:6)
01h
00b
01b
00b
01b
10b
RO
Scc Register Value
01h (IDE Controller)
SCC Default Register
Description
Description
Description
06h (AHCI Controller)
06h (AHCI Controller)
04h (RAID Controller)
SCC Register Value
01h (IDE Controller)
01h (IDE Controller)
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Value
SATA Controller Registers (D31:F2)
RO
8 bits
RO
8 bits
RO
8 bits
Intel
®
ICH8 Family Datasheet