NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 318
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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8.1.21
8.1.22
318
PMCS—PCI Power Management Control and Status
Register (Gigabit LAN—D25:F0)
Address Offset: CCh
Default Value:
DR—Data Register
(Gigabit LAN—D25:F0)
Address Offset: CFh
Default Value:
14:13
12:9
7:2
1:0
7:0
Bit
Bit
15
8
PME Status (PMES) — R/WC. This bit is set to 1 when the function detects a wake-up
event independent of the state of the PMEE bit. Writing a 1 will clear this bit.
Data Scale (DSC) — R/W. This field indicates the scaling factor to be used when
interpreting the value of the Data register.
For the GbE LAN and common functions this field equals 01b (indicating 0.1 watt units)
if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7, (or 8 for
Function 0). Else it equals 00b.
For the manageability functions, this field equals 10b (indicating 0.01 watt units) if the
PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7; otherwise, it
equals 00b.
Data Select (DSL) — R/W. This four-bit field is used to select which data is to be
reported through the Data register (offset CFh) and Data_Scale field. These bits are
writeable only when the Power Management is enabled via NVM.
0h = D0 Power Consumption
3h = D3 Power Consumption
4h = D0 Power Dissipation
7h = D3 Power Dissipation
8h = Common Power
All other values are reserved.
PME Enable (PMEE) — R/W. If Power Management is enabled in the NVM, writing a 1
to this register will enable Wakeup. If Power Management is disabled in the NVM,
writing a 1 to this bit has no affect, and will not set the bit to 1.
Reserved - Returns a value of ‘000000’.
Power State (PS) — R/W. This field is used both to determine the current power state
of the Gb LAN Controller and to set a new power state. The values are:
00 = D0 state (default)
01 = Ignored
10 = Ignored
11 = D3 state (Power Management must be enables in the NVM or this cycle will be
Reported Data (RD) — RO. This register is used to report power consumption and heat
dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh,
bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS (Offset
CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled in the
NVM or with a default value of 0x00 otherwise.
ignored).
See bit description
See bit description
–
CDh
Description
Description
Attribute:
Size:
Attribute:
Size:
Gigabit LAN Configuration Registers
R/WC, R/W, RO
16 bits
RO
8 bits
Intel
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