NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 759
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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Serial Peripheral Interface (SPI)
20.1.19
20.1.20
Note:
Intel
®
ICH8 Family Datasheet
PREOP—Prefix Opcode Configuration Register
(
Memory Address:SPIBAR + 94h
Default Value:
NOTE: This register is not writable when the Flash Configuration Lock-Down bit (SPIBAR +
OPTYPE—Opcode Type Configuration Register
(
Memory Address:SPIBAR + 96h
Default Value:
Entries in this register correspond to the entries in the Opcode Menu Configuration
register.
The definition below only provides write protection for opcodes that have addresses
associated with them. Therefore, any erase or write opcodes that do not use an address
should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte
Program”)
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
15:14
13:12
11:10
SPI Memory Mapped Configuration Registers
SPI Memory Mapped Configuration Registers
15:8
7:0
9:8
7:6
5:4
3:2
1:0
Bit
Bit
04h:15) is set.
is set.
Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
Opcode Type 7 — R/W. See the description for bits 1:0
Opcode Type 6 — R/W. See the description for bits 1:0
Opcode Type 5 — R/W. See the description for bits 1:0
Opcode Type 4 — R/W. See the description for bits 1:0
Opcode Type 3 — R/W. See the description for bits 1:0
Opcode Type 2 — R/W. See the description for bits 1:0
Opcode Type 1 — R/W. See the description for bits 1:0
Opcode Type 0 — R/W. This field specifies information about the corresponding
Opcode 0. This information allows the hardware to 1) know whether to use the address
field and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the
two bits is:
00 = No address associated with this Opcode; Read cycle type
01 = No address associated with this Opcode; Write cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
0000h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
)
)
R/WL
16 bits
R/W
16 bits
759
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