NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 571

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

UHCI Controllers Registers
14.1.13
14.1.14
14.1.15
Intel
®
ICH8 Family Datasheet
SID — Subsystem Identification Register
(USB—D29:F0/F1/F2/F3, D26:F0/F1)
Address Offset: 2Eh
Default Value:
Lockable:
INT_LN—Interrupt Line Register
(USB—D29:F0/F1/F2, D26:F0/F1)
Address Offset:
Default Value:
INT_PN—Interrupt Pin Register
(USB—D29:F0/F1/F2/F3, D26:F0/F1)
Address Offset:
Default Value:
15:0
7:0
7:0
Bit
Bit
Bit
Subsystem ID (SID) — R/WO. BIOS sets the value in this register to identify the
Subsystem ID. The SID register, in combination with the SVID register (D29:F0/F1/F2,
D26:F0/F1:2C), enables the operating system to distinguish each subsystem from
other(s). The value read in this register is the same as what was written to the IDE_SID
register.
NOTE: The software can write to this register only once per core well reset. Writes
Interrupt Line (INT_LN) — RO. This data is not used by the ICH8. It is to
communicate to software the interrupt line that the interrupt pin is connected to.
Interrupt Line (INT_LN) — RO. This value tells the software which interrupt pin each
USB host controller uses. The upper 4 bits are hardwired to 0000b; the lower 4 bits are
determine by the Interrupt Pin default values that are programmed in the memory-
mapped configuration space as follows:
UHCI #1 - D29IP.U0P (Chipset Config Registers:Offset 3108:bits 3:0)
UHCI #2 - D29IP.U1P (Chipset Config Registers:Offset 3108:bits 7:4)
UHCI #3 - D29IP.U2P (Chipset Config Registers:Offset 3108:bits 11:8)
UHCI #4 - D26IP.U0P (Chipset Config Registers:Offset 3114:bits 3:0)
UHCI #5 - D26IP.U1P (Chipset Config Registers:Offset 3114:bits 7:4)
NOTE: This does not determine the mapping to the PIRQ pins.
should be done as a single, 16-bit cycle.
0000h
No
–
3Ch
00h
3Dh
See Description
2Fh
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Attribute:
Size:
R/WO
16 bits
Core
R/W
8 bits
RO
8 bits
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