NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 14
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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14
9.5
9.6
9.7
9.8
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10 ELCR1—Master Controller Edge/Level Triggered Register
9.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................ 364
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
Real Time Clock Registers (LPC I/F—D31:F0)....................................................... 369
9.6.1
9.6.2
Processor Interface Registers (LPC I/F—D31:F0) .................................................. 374
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
Power Management Registers (PM—D31:F0) ....................................................... 377
9.8.1
ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 359
ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0) ................................................................................ 359
OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0) .................................................................... 360
OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0) ................................................................................ 360
OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0) ................................................................................ 361
(LPC I/F—D31:F0) ................................................................................ 362
(LPC I/F—D31:F0) ................................................................................ 363
APIC Register Map (LPC I/F—D31:F0)...................................................... 364
IND—Index Register (LPC I/F—D31:F0) ................................................... 364
DAT—Data Register (LPC I/F—D31:F0) .................................................... 365
EOIR—EOI Register (LPC I/F—D31:F0) .................................................... 365
ID—Identification Register (LPC I/F—D31:F0) ........................................... 366
VER—Version Register (LPC I/F—D31:F0) ................................................ 366
REDIR_TBL—Redirection Table (LPC I/F—D31:F0) ..................................... 367
I/O Register Address Map (LPC I/F—D31:F0) ............................................ 369
Indexed Registers (LPC I/F—D31:F0) ...................................................... 370
9.6.2.1
9.6.2.2
9.6.2.3
9.6.2.4
NMI_SC—NMI Status and Control Register
(LPC I/F—D31:F0) ................................................................................ 374
NMI_EN—NMI Enable (and Real Time Clock Index)
Register (LPC I/F—D31:F0) .................................................................... 375
PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) ............................. 375
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0) ................................................................................ 376
RST_CNT—Reset Control Register (LPC I/F—D31:F0)................................. 376
Power Management PCI Configuration Registers
(PM—D31:F0) ...................................................................................... 377
9.8.1.1
9.8.1.2
9.8.1.3
9.8.1.4
9.8.1.5
9.8.1.6
9.8.1.7
RTC_REGA—Register A (LPC I/F—D31:F0) .................................. 371
RTC_REGB—Register B (General Configuration)
(LPC I/F—D31:F0) ................................................................... 372
RTC_REGC—Register C (Flag Register)
(LPC I/F—D31:F0) ................................................................... 373
RTC_REGD—Register D (Flag Register)
(LPC I/F—D31:F0) ................................................................... 373
GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0) ......................................................................... 378
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0) ......................................................................... 380
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0) ......................................................................... 381
GEN_PMCON_LOCK—General Power Management
Configuration Lock Register ...................................................... 383
Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0) (Mobile Only) ..................................................... 384
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile Only) ..................................................... 385
BM_BREAK_EN Register (PM—D31:F0) (Mobile Only) ................... 386
Intel
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ICH8 Family Datasheet
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