NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 602

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NH82801HEM S LA5R

Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801HEM S LA5R

Lead Free Status / RoHS Status
Compliant
15.1.30
15.1.31
602
EHCIIR1—EHCI Initialization Register 1 (Mobile Only)
(USB EHCI—D29:F7, D26:F7)
Address Offset:
Default Value:
EHCIIR2—EHCI Initialization Register 2
(USB EHCI—D29:F7, D26:F7)
Address Offset:
Default Value:
31:30
28:18
16:0
7:5
3:0
Bit
Bit
29
17
4
Reserved
Pre-fetch Based Pause Disable – R/W.
0 = Pre-fetch Based Pause is enabled
1 = Pre-fetch Based Pause is disabled.
Reserved
Reserved
EHCIIR2 Field 2 — R/W. BIOS must set this bit
Reserved
EHCIIR2 Field 1 — R/W. BIOS must set this bit
Reserved
84h
20001706h
01h
FCh
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
R/W, R/WL
8 bits
R/W
32 bits
Intel
®
ICH8 Family Datasheet

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