NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 243

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.23
Note:
5.23.1
Intel
®
ICH8 Family Datasheet
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially
lower-cost alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(CS#).
The ICH8 supports two SPI flash devices using two separate Chip Select pins. Each SPI
flash device can be up to 16 MBytes. The ICH8 SPI interface supports 20 MHz and 33
MHz SPI devices.
Communication on the SPI bus is done with a Master – Slave protocol. The Slave is
connected to the ICH8 and is implemented as a tri-state bus.
When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by the ICH8, LPC based BIOS flash is disabled.
SPI Supported Feature Overview
SPI Flash on the ICH8 has two operational modes, descriptor and non-descriptor. Non-
descriptor mode is similar to flash functionality of Intel
can only be used for BIOS. Direct read and writes are not supported. BIOS has read/
write access only through register accesses. Through those register accesses BIOS can
read and write to the entire flash without security checking.
for the integrated GbE, Manageability Engine, chipset soft straps, as well multiple SPI
Flash components.
Descriptor Mode enables many new features of the chipset
In Descriptor Mode the Flash is divided into four separate regions:
Only three masters can access the four regions: Host CPU running BIOS code,
Integrated GbE and Host CPU running GbE Software, and ME. The Flash Descriptor is
requires one 4KB Block/Sector. The Integrated GbE needs two 4KB Blocks/Sectors.
BIOS and the Manageability Engine (ME) are the other two regions. The only required
region is Region 0, the Flash Descriptor. Region 0 must be located in the first sector of
component 0 (offset 0).
0
1
2
3
• Integrated GbE and Host CPU for GbE Software
• Intel Active Management Technology (ICH8DO and ICH8M-E Only)
• Intel
• Supports two SPI Flash components using two separate chip select pins
• Hardware enforced security restricting master accesses to different regions
• Chipset Soft Strap region provides the ability to use Flash NVM as an alternative to
• Supports the SPI Fast Read instruction and frequencies of 33 MHz
• Uses standardized Flash Instruction Set
Region
hardware pull-up/pull-down resistors for both ICH and MCH
®
Quiet System Technology (Desktop Only)
Flash Descriptor
BIOS
ME
GbE
Content
®
ICH7. In this mode, SPI Flash
There is also no support
243