NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 767
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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Serial Peripheral Interface (SPI)
20.2.3
20.2.3.1
20.2.3.2
Intel
®
ICH8 Family Datasheet
Flash Descriptor Region Section
The following section of the Flash Descriptor is used to identify the different Flash
Regions
Flash Regions:
FLREG0—Flash Region 0 (Flash Descriptor) Register
(Flash Descriptor Memory Mapped Configuration Registers)
Memory Address:FRBA + 000h
FLREG1—Flash Region 1 (BIOS) Register
(Flash Descriptor Memory Mapped Configuration Registers)
Memory Address:FRBA + 004h
31:29
28:16
15:13
12:0
31:29
28:16
15:13
12:0
• If a particular region is not using SPI Flash, the particular region should be disabled
• For each region except FLREG0, the Flash Controller must have a default Region
Bits
Bits
by setting the Region Base to all 1's, and the Region Limit to all 0's (base is higher
than the limit)
Base of FFFh and the Region Limit to 000h within the Flash Controller in case the
Number of Regions specifies that a region is not used.
Reserved
Region Limit: This field specifies address bits 24:12 for the Region Limit.
Reserved
Region Base: This specifies address bits 24:12 for the Region Base.
Reserved
Region Limit: This field specifies address bits 24:12 for the Region Limit.
Reserved
Region Base: This specifies address bits 24:12 for the Region Base.
NOTE: If the BIOS region is not used, the Region Base must be programmed to 1FFFh
and the Region Limit to 0000h to disable the region.
Description
Description
Size:
Size:
32 bits
32 bits
767
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