NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 756
NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
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20.1.15
Note:
20.1.16
Note:
756
PR3—Protected Range 3 Register
(
Memory Address:SPIBAR + 80h
Default Value:
This register can not be written when the FLOCKDN bit is set to 1.
PR4—Protected Range 4 Register
(
Memory Address:SPIBAR + 84h
Default Value:
This register can not be written when the FLOCKDN bit is set to 1.
28:16
28:16
30:29
14:13
30:29
14:13
SPI Memory Mapped Configuration Registers
SPI Memory Mapped Configuration Registers
12:0
12:0
Bit
Bit
31
15
31
15
Write Protection Enable: — R/WL. When set, this bit indicates that the Base and
Limit fields in this register are valid and that writes and erases directed to addresses
between them (inclusive) must be blocked by hardware. The base and limit fields are
ignored when this bit is cleared.
Reserved
Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable: — R/WL. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
Reserved
Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
Write Protection Enable: — R/WL. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
Reserved
Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable: — R/WL. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
(inclusive) must be blocked by hardware. The base and limit fields are ignored when this
bit is cleared.
Reserved
Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
000h for the base comparison. Any address less than the value programmed in this field
is unaffected by this protected range.
00000000h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
)
)
Serial Peripheral Interface (SPI)
R/WL
32 bits
R/WL
32 bits
Intel
®
ICH8 Family Datasheet
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