NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 147

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
Table 53.
5.9.3
5.9.4
Note:
Intel
®
ICH8 Family Datasheet
APIC Interrupt Mapping (Sheet 2 of 2)
NOTES:
1.
2.
3.
PCI / PCI Express* Message-Based Interrupts
When external devices through PCI / PCI Express wish to generate an interrupt, they
will send the message defined in the PCI Express* Base Specification, Revision 1.0a for
generating INTA# - INTD#. These will be translated internal assertions/de-assertions of
INTA# - INTD#.
Front Side Bus Interrupt Delivery
For processors that support Front Side Bus (FSB) interrupt delivery, the ICH8 requires
that the I/O APIC deliver interrupt messages to the processor in a parallel manner,
rather than using the I/O APIC serial scheme.
This is done by the ICH8 writing (via DMI) to a memory location that is snooped by the
processor(s). The processor(s) snoop the cycle to know which interrupt goes active.
The following sequence is used:
FSB Interrupt Delivery compatibility with processor clock control depends on the
processor, not the ICH8.
IRQ #
1. When the ICH8 detects an interrupt event (active edge for edge-triggered mode or
2. Internally, the ICH8 requests to use the bus in a way that automatically flushes
3. The ICH8 then delivers the message by performing a write cycle to the appropriate
15
16
17
18
19
20
21
22
23
a change for level-triggered mode), it sets or resets the internal IRR bit associated
with that interrupt.
upstream buffers. This can be internally implemented similar to a DMA device
request.
address with the appropriate data. The address and data formats are described
below in
Mobile Only: IDEIRQ can only be driven directly from the pin when in legacy IDE mode.
When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources, while interrupts 16 through 23
receive active-low internal interrupt sources.
If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other
devices to assure the proper operation of HPET #2. ICH8 hardware does not prevent
sharing of IRQ 11.
SERIRQ
PIRQD#
PIRQA#
PIRQB#
PIRQC#
Via
N/A
N/A
N/A
N/A
Yes
Section
from Pin
PIRQD#
PIRQG#
5.9.4.4.
PIRQA#
PIRQB#
PIRQC#
PIRQE#
PIRQH#
PIRQF#
Direct
Yes
Message
Via PCI
Yes
Yes
Yes
Mobile Only: IDEIRQ (legacy mode — combined,
mapped as secondary), SATA Secondary (legacy
mode)
Internal devices are routable; see
though
Option for SCI, TCO, HPET #0,1,2. Other internal
devices are routable; see
Section
Section
7.1.58.
Internal Modules
7.1.58.
Section 7.1.52
Section 7.1.52
through
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