NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 724

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

18.1.44
724
PMCS—PCI Power Management Control and Status
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: A4h
Default Value:
31:24
21:16
14:9
7:2
1:0
Bit
23
22
15
8
Reserved
Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base
Specification, Revision 1.0a.
B2/B3 Support (B23S) — Reserved per PCI Express* Base Specification, Revision 1.0a.
Reserved
PME Status (PMES) — RO.
0 = PME Not received.
1 = PME was received on the downstream link.
Reserved
PME Enable (PMEE) — R/W. The root port takes no action on this bit, but it must be
R/W for some legacy operating systems to enable PME# on devices connected to this
root port.
This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which
is not asserted during a warm reset.
0 = Disable
1 = Enable
Reserved
Power State (PS) — R/W. This field is used both to determine the current power state
of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3
NOTE: When in the D3
the I/O and memory spaces are not. Type 1 configuration cycles are also not
accepted. Interrupts are not required to be blocked as software will disable
interrupts prior to placing the port into D3
‘10’ or ‘01’ to these bits, the write will be ignored.
HOT
00000000h
state
–
A7h
HOT
state, the controller’s configuration space is available, but
Description
Attribute:
Size:
HOT
PCI Express* Configuration Registers
. If software attempts to write a
R/W, RO
32 bits
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®
ICH8 Family Datasheet