NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 549
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
- Current page: 549 of 890
- Download datasheet (7Mb)
SATA Controller Registers (D31:F5)
13.1.22
Note:
13.1.23
Note:
Intel
®
ICH8 Family Datasheet
D1TIM—Device 1 IDE Timing Register (SATA–D31:F5)
Address Offset: 44h
Default Value:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. Device 1 is not allowed on this
controller.
SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F5)
Address Offset: 48h
Default Value:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
7:0
Bit
7:3
Bit
2
1
0
Reserved
Reserved
Secondary Drive 0 ATAxx Enable (SDAE0) — R/W.
0 = Disable (default)
1 = Enable DMA timing modes for the secondary master device.
Reserved
Primary Drive ATAxx Enable (PDAE0) — R/W.
0 = Disable (default)
1 = Enable DMA timing modes for the primary master device
00h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W
8 bits
549
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