NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 680

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

17.2.17
17.2.18
17.2.19
680
CORBLBASE—CORB Lower Base Address Register
(Intel
Memory Address:HDBAR + 40h
Default Value:
CORBUBASE—CORB Upper Base Address Register
(Intel
Memory Address:HDBAR + 44h
Default Value:
CORBWP—CORB Write Pointer Register
(Intel
Memory Address:HDBAR + 48h
Default Value:
31:7
31:0
15:8
6:0
7:0
Bit
Bit
Bit
CORB Lower Base Address — R/W. This field provides the lower address of the
Command Output Ring Buffer, allowing the CORB base address to be assigned on any
128-B boundary. This register field must not be written when the DMA engine is
running or the DMA transfer may be corrupted.
CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the CORB
to be allocated with 128B granularity to allow for cache line fetch optimizations.
CORB Upper Base Address — R/W. This field provides the upper 32 bits of the
address of the Command Output Ring buffer. This register field must not be written
when the DMA engine is running or the DMA transfer may be corrupted.
Reserved.
CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this
field in DWord granularity. The DMA engine fetches commands from the CORB until the
Read pointer matches the Write pointer; supports 256 CORB entries (256x4B = 1 KB).
This register field may be written when the DMA engine is running.
®
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00000000h
00000000h
0000h
Intel
®
Description
Description
Description
High Definition Audio Controller Registers (D27:F0)
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
R/W
32 bits
R/W
16 bits
Intel
®
ICH8 Family Datasheet