NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 81

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Signal Description
Table 23.
2.20
Table 24.
Intel
®
ICH8 Family Datasheet
Intel
NOTES:
1.
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Signals
HDA_DOCK_RST#
HDA_SDIN[3:0]
HDA_DOCK_EN#
SPI_CS0#
SPI_CS1#
SPI_MISO
SPI_MOSI
(Mobile Only) /
(Mobile Only) /
HDA_SDOUT
SPI_CLK
Name
®
GPIO33
GPIO34
Name
Some signals have integrated pull-ups or pull-downs. Consult table in
details.
High Definition Audio Link Signals (Sheet 2 of 2)
Type
I/O
O
O
O
I
Type
I/O
I/O
O
I
SPI Chip Select 0: Used as the SPI bus request signals.
SPI Chip Select 1: Used as the SPI bus request signals. This signal
is also used as Boot BIOS destination selection strap with GNT0#.
SPI Master IN Slave OUT: Data input pin for ICH8.
SPI Master OUT Slave IN: Data output pin for ICH8.
SPI Clock: SPI clock signal, during idle the bus owner will drive the
clock signal low. 17.86 MHz and 31.25 MHz.
Intel High Definition Audio Serial Data Out: This signal is the
serial TDM data output to the codec(s). This serial output is
double-pumped for a bit rate of 48 Mb/s for Intel High Definition
Audio.
NOTE: HDA_SDOUT is sampled at the rising edge of PWROK as a
Intel High Definition Audio Serial Data In [3:0]: These
signals are serial TDM data inputs from the codecs. The serial input
is single-pumped for a bit rate of 24 Mb/s for Intel
Audio. These signals have integrated pull-down resistors, which
are always enabled.
High Definition Audio Dock Enable: This signal controls the
external Intel HD Audio docking isolation logic. This is an active
low signal. When deasserted the external docking switch is in
isolate mode. When asserted the external docking switch
electrically connects the Intel HD Audio dock signals to the
corresponding Intel
This signal is shared with GPIO33. This signal defaults to GPIO33
mode after PLTRST# reset and will be in the high state after
PLTRST# reset. BIOS is responsible for configuring GPIO33 to
HDA_DOCK_EN# mode.
High Definition Audio Dock Reset: This signal is a dedicated
HDA_RST# signal for the codec(s) in the docking station. Aside
from operating independently from the normal HDA_RST# signal,
it otherwise works similarly to the HDA_RST# signal.
This signal is shared with GPIO34. This signal defaults to GPIO34
mode after PLTRST# reset and will be in the low state after
PLTRST# reset. BIOS is responsible for configuring GPIO34 to
HDA_DOCK_RST# mode.
functional strap. See
is a weak integrated pull-down resistor on the HDA_SDOUT
pin.
®
ICH8 signals.
Description
Description
Section 2.26.1
for more details. There
Section 3.1
®
High Definition
for
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