NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 833
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NH82801HEM S LA5R
Manufacturer Part Number
NH82801HEM S LA5R
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LA5R.pdf
(890 pages)
Specifications of NH82801HEM S LA5R
Lead Free Status / RoHS Status
Compliant
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Electrical Characteristics
Table 156.
Intel
®
ICH8 Family Datasheet
Clock Timings (Sheet 2 of 2)
NOTES:
1.
2.
3.
4.
5.
6.
tglanclk
f susclk
tglanhi
tglanlo
tsatasl
tglansl
fpwm
Sym
t39a
t36
t37
t38
t39
SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN)
The CLK48 expects a 40/60% duty cycle.
The maximum high time (t18 Max) provide a simple assured method for devices to detect
bus idle conditions.
BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
SUSCLK duty cycle can range from 30% minimum to 70% maximum.
CLK14 edge rates in a system as measured from 0.8 V to 2.0 V.
The active frequency can be 5 MHz, 50 MHz or 62.5 MHz depending on the interface speed.
Dynamic changes of the normal operating frequency are not allowed.
Period
Rise time
Fall time
Slew rate
Operating Frequency
High Time
Low Time
Operating Frequency
High Time
Low Time
Slew rate
PWM Operating Frequency
Parameter
Gigabit Internet Clock (GLAN_CLK)
Suspend Clock (SUSCLK)
Fan Speed Controller
9.997
Min
175
175
2.5
8.5
8.5
1.0
10
10
10
5
32
10.0533
28,000
Max
62.5
700
700
—
—
—
—
8
4
Unit
V/ns
V/ns
MHz
kHz
Hz
ns
ps
ps
us
us
ns
ns
Notes
4
4
4
6
Figure
833
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