NH82801HEM S LA5R Intel, NH82801HEM S LA5R Datasheet - Page 185

• Manufacturer Part Number: NH82801HEM S LA5R
• Manufacturer: Intel

Specifications of NH82801HEM S LA5R

• Lead Free Status / RoHS Status: Compliant

Functional Description
Note:
Note:
5.14.1.3
5.14.2
5.14.2.1
Note:
Intel
®
ICH8 Family Datasheet
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written
as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes
inactive. Note that this is slightly different than a classic sticky bit, since most sticky
bits would remain active indefinitely when the signal goes active and would
immediately go inactive when a 1 is written to the bit.
The INTRD_DET bit resides in the ICH8’s RTC well, and is set and cleared
synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET
(by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65
µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be
asserted for a minimum of 1 ms to assure that the INTRD_DET bit will be set.
If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET
bit, the bit remains set and the SMI is generated again immediately. The SMI handler
can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal
goes inactive and then active again, there will not be further SMIs, since the
INTRD_SEL bits would select that no SMI# be generated.
Detecting Improper Firmware Hub Programming
The ICH8 can detect the case where the BIOS flash is not programmed. This results in
the first instruction fetched to have a value of FFh. If this occurs, the ICH8 sets the
BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.
TCO Modes
TCO Legacy/Compatible Mode
In TCO Legacy/Compatible mode the Intel Management Engine and Intel AMT logic and
SMBus controllers are disabled. To enable Legacy/Compatible TCO mode the TCOMODE
bit 7 in the ICHSTRP0 register in the SPI device must be 0. See
details.
SMBus and SMLink may be tied together externally, if a device has a single SMBus
interface and needs access to the TCO slave and be visible to the host SMBus controller.
Section 20.2.5.1
for
185